Semiconductor memory typically includes a memory array comprising a plurality of memory cells coupled to an arrangement of word lines and bit lines, each memory cell being coupled to a corresponding unique word line and bit line pair. There may be a plurality of memory cells coupled to a given word line and/or a given bit line. A term “word line” as used in a description of a memory array is sometimes referred to as a “row.” Similarly, a term “bit line” in a memory array description is sometimes referred to as a “column.” The terms “word line” and “bit line” as used herein are intended to have a same meaning as, and may therefore be used interchangeably with, the terms “row” and “column,” respectively.
A word line driver logic is typically coupled to each word line in a semiconductor memory. Within a memory array, one word line is typically activated (i.e., in an active mode) at a given time to access (e.g., read, write or refresh) memory cells coupled to an activated word line. At that time, other word lines in the memory array remain inactive (i.e., in a standby mode). A voltage on an activated word line is controlled by a word line driver coupled to the activated word line. Deactivated word lines are each held at a standby voltage level by corresponding word line driver coupled to the deactivated word lines. A selection of an active word line is determined by a word line address signal supplied to a word line decoder in a memory array. A word line decoder selectively activates a word line driver coupled to an addressed word line. A design and operation of conventional memory arrays and conventional semiconductor memory is well known in the art.
It is often desirable, particularly in a dynamic random access memory (DRAM), to apply a higher voltage to a memory cell when writing the cell to a logic high state. A use of higher write voltages advantageously enables the memory cell to store more charge or, in other words, more signal. With more signal, various combinations of improvements in memory capacity (i.e., density), latency, cycle time, and retention time, etc., may be realized. Unfortunately, higher voltages applied to memory cells can damage transistors associated with these cells over time. For this reason, reliability limitations are specified for field-effect transistors (FETs) in order to constrain voltages across source-to-drain regions and gate-to-source/drain regions so that these transistors, operated under such constraints, will not experience breakdown during an operable lifetime. These reliability constraints, however, limit conventional semiconductor memory from achieving the above-stated benefits of using higher word line voltages.